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Fix order of the bit fields of the register definitions

Bernd Gottschlag 5 years ago
parent
commit
780cedcbc4

+ 0
- 2
weather-sensor/firmware/main.c View File

77
 	while(1)
77
 	while(1)
78
 	{
78
 	{
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 		Send_Test_Message();
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 		Send_Test_Message();
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-		sprintf(debugString, "%s\r\n", "test message");
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-		Print_Debug_String(debugString);
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 		_delay_ms(1000);
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 		_delay_ms(1000);
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 	}
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 	}
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 }
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 }

+ 8
- 12
weather-sensor/firmware/nrf24l01.c View File

102
 {
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 {
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 	uint8_t buffer[4] = {0xDE, 0xAD, 0xBE, 0xEF};
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 	uint8_t buffer[4] = {0xDE, 0xAD, 0xBE, 0xEF};
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 	bool transmissionFinished = false;
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 	bool transmissionFinished = false;
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-	uint8_t statusContent = 0;
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105
 
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-	uint8_t registerContent[5];
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 	STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
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 	STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
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 	uint8_t lengthRead;
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 	uint8_t lengthRead;
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 	char debugString[50] = "";
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 	char debugString[50] = "";
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 			Print_Debug_String(debugString);
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 			Print_Debug_String(debugString);
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 		}
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 		}
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136
 
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-		if (statusRegisterContent.bits.TX_DS == true)
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+		if (statusRegisterContents.bits.TX_DS == 1)
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 		{
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 		{
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 			transmissionFinished = true;
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 			transmissionFinished = true;
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 			sprintf(debugString, "%s\r\n", "TX fin");
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 			sprintf(debugString, "%s\r\n", "TX fin");
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 			Print_Debug_String(debugString);
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 			Print_Debug_String(debugString);
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 		}
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 		}
145
 
143
 
146
-		if (statusRegisterContent.bits.MAX_RT == true)
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+		if (statusRegisterContents.bits.MAX_RT == 1)
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 		{
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 		{
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-			transmissionFinished = true;
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+			transmissionFinished = true; //TODO: indicate failure
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 			sprintf(debugString, "%s\r\n", "max ret");
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 			sprintf(debugString, "%s\r\n", "max ret");
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 			Print_Debug_String(debugString);
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 			Print_Debug_String(debugString);
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 		}
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 		}
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150
 		
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-		timeout ++;
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+		timeout ++; // TODO: this should work without the time out, as MAX_RT should be triggered if no ACK is received
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 	} while ((transmissionFinished == false) && (timeout < 0xFF));
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 	} while ((transmissionFinished == false) && (timeout < 0xFF));
155
 
153
 
156
 	if (timeout >= 0xFF)
154
 	if (timeout >= 0xFF)
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 	}
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 	}
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159
 
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 	/* Reset the interrupts */
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 	/* Reset the interrupts */
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-	lengthRead = Read_NRF_Register(STATUS_ADDRESS, statusRegisterContents); /* TODO: use status register read function */
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-	statusContent = registerContent[0] & 0x0F;
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-	statusRegisterContents.bits.RX_DR = false;
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-	statusRegisterContents.bits.TX_DS = false;
167
-	statusRegisterContents.bits.MAX_RT = false;
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-	Write_NRF_Register(STATUS_ADDRESS, statusContent);
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+	lengthRead = Read_NRF_Register(STATUS_ADDRESS, &(statusRegisterContents.byte)); /* TODO: use status register read function */
162
+	statusRegisterContents.bits.TX_DS = 1;
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+	statusRegisterContents.bits.MAX_RT = 1;
164
+	Write_NRF_Register(STATUS_ADDRESS, statusRegisterContents.byte);
169
 
165
 
170
 	// TODO: flush FIFO if an error occured
166
 	// TODO: flush FIFO if an error occured
171
 }
167
 }

+ 24
- 22
weather-sensor/firmware/nrf24l01_definitions.h View File

139
 #define RF_OUTPUT_POWER_MINUS_16DBM
139
 #define RF_OUTPUT_POWER_MINUS_16DBM
140
 #define RF_OUTPUT_POWER_0DBM
140
 #define RF_OUTPUT_POWER_0DBM
141
 
141
 
142
+// TODO: change order of all bit fields!!!
143
+
142
 /* STATUS */
144
 /* STATUS */
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 typedef union
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 typedef union
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 {
146
 {
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 	uint8_t byte;
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 	uint8_t byte;
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 	struct
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 	struct
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 	{
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 	{
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-		 uint8_t RESERVED : 1;
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-		 uint8_t TX_DR    : 1;
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-		 uint8_t TX_DS    : 1;
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-		 uint8_t MAX_RT   : 1;
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-		 uint8_t RX_P_NO  : 3;
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 		 uint8_t TX_FULL  : 1;
150
 		 uint8_t TX_FULL  : 1;
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+		 uint8_t RX_P_NO  : 3;
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+		 uint8_t MAX_RT   : 1;
153
+		 uint8_t TX_DS    : 1;
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+		 uint8_t RX_DR    : 1;
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+		 uint8_t RESERVED : 1;
154
 	}bits;
156
 	}bits;
155
 }STATUS_REGISTER;
157
 }STATUS_REGISTER;
156
 
158
 
162
 	uint8_t byte;
164
 	uint8_t byte;
163
 	struct
165
 	struct
164
 	{
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 	{
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-		 uint8_t PLOS_CNT : 4;
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 		 uint8_t ARC_CNT  : 4;
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 		 uint8_t ARC_CNT  : 4;
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+		 uint8_t PLOS_CNT : 4;
167
 	}bits;
169
 	}bits;
168
 }OBSERVE_TX_REGISTER;
170
 }OBSERVE_TX_REGISTER;
169
 
171
 
173
 	uint8_t byte;
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 	uint8_t byte;
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 	struct
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 	struct
175
 	{
177
 	{
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-		 uint8_t RESERVED : 7;
177
 		 uint8_t CD : 1;
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 		 uint8_t CD : 1;
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+		 uint8_t RESERVED : 7;
178
 	}bits;
180
 	}bits;
179
 }CD_REGISTER;
181
 }CD_REGISTER;
180
 
182
 
195
 	uint8_t byte;
197
 	uint8_t byte;
196
 	struct
198
 	struct
197
 	{
199
 	{
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-		 uint8_t RESERVED0 : 1;
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-		 uint8_t TX_REUSE : 1;
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-		 uint8_t TX_FULL  : 1;
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-		 uint8_t TX_EMPTY : 1;
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-		 uint8_t RESERVED1 : 2;
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-		 uint8_t RX_FULL  : 1;
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 		 uint8_t RX_EMPTY : 1;
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 		 uint8_t RX_EMPTY : 1;
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+		 uint8_t RX_FULL  : 1;
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+		 uint8_t RESERVED1 : 2;
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+		 uint8_t TX_EMPTY : 1;
204
+		 uint8_t TX_FULL  : 1;
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+		 uint8_t TX_REUSE : 1;
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+		 uint8_t RESERVED0 : 1;
205
 	}bits;
207
 	}bits;
206
 }FIFO_STATUS_REGISTER;
208
 }FIFO_STATUS_REGISTER;
207
 
209
 
211
 	uint8_t byte;
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 	uint8_t byte;
212
 	struct
214
 	struct
213
 	{
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 	{
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-		 uint8_t RESERVED : 2;
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-		 uint8_t DPL_P5   : 1;
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-		 uint8_t DPL_P4   : 1;
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-		 uint8_t DPL_P3   : 1;
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-		 uint8_t DPL_P2   : 1;
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-		 uint8_t DPL_P1   : 1;
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 		 uint8_t DPL_P0   : 1;
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 		 uint8_t DPL_P0   : 1;
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+		 uint8_t DPL_P1   : 1;
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+		 uint8_t DPL_P2   : 1;
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+		 uint8_t DPL_P3   : 1;
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+		 uint8_t DPL_P4   : 1;
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+		 uint8_t DPL_P5   : 1;
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+		 uint8_t RESERVED : 2;
221
 	}bits;
223
 	}bits;
222
 }DYNPD_REGISTER;
224
 }DYNPD_REGISTER;
223
 
225
 
227
 	uint8_t byte;
229
 	uint8_t byte;
228
 	struct
230
 	struct
229
 	{
231
 	{
230
-		 uint8_t RESERVED   : 5;
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-		 uint8_t EN_DPL     : 1;
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-		 uint8_t EN_ACK_PAY : 1;
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 		 uint8_t EN_DYN_ACK : 1;
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 		 uint8_t EN_DYN_ACK : 1;
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+		 uint8_t EN_ACK_PAY : 1;
234
+		 uint8_t EN_DPL     : 1;
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+		 uint8_t RESERVED   : 5;
234
 	}bits;
236
 	}bits;
235
 }FEATURE_REGISTER;
237
 }FEATURE_REGISTER;
236
 
238
 

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