Shuffle almost everything around to prepare for better modularity.

.gitignore

@@ -2,9 +2,11 @@
 *.kicad_pcb-bak
 *.sch-bak
 *.kicad_prl
-/hackamp/firmware/target
-/hackamp/hardware/hackamp-backups
-/modules/tas5760m-amp-module/tas5760m-amp-module-backups
-/frontpanel/frontpanel-backups
-/other/debounce-calculator/target
+/software/debounce-calculator/target
+/software/wired/target
+/hardware/base/base-backups
+/hardware/wired/wired-backups
+/hardware/wireless/wireless-backups
+/hardware/speakers/speakers-backups
+/hardware/frontpanel/frontpanel-backups
 fp-info-cache

hackamp/hardware/fp-lib-table

@@ -1,3 +0,0 @@
-(fp_lib_table
-  (lib (name HackAmp-Footprints)(type KiCad)(uri ${KIPRJMOD}/HackAmp-Footprints.pretty)(options "")(descr ""))
-)

hardware/base/fp-lib-table

@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name "HackAmp-Footprints")(type "KiCad")(uri "${KIPRJMOD}/HackAmp-Footprints.pretty")(options "")(descr ""))
+)

software/wired/src/halext/sai.rs

@@ -0,0 +1,609 @@
+//! SAI interface with DMA data transfer.
+
+// TODO: Unify capitalization of template parameters.
+
+use core::marker::PhantomData;
+use core::ops::Deref;
+
+use stm32f4xx_hal::gpio::gpiod::PD6;
+use stm32f4xx_hal::gpio::gpioe::{PE2, PE3, PE4, PE5, PE6};
+use stm32f4xx_hal::gpio::gpiof::{PF6, PF7, PF8, PF9};
+use stm32f4xx_hal::gpio::{Alternate, AF6};
+use stm32f4xx_hal::stm32::sai::CH;
+use stm32f4xx_hal::stm32::{RCC, SAI};
+
+use super::i2s::I2SClocks;
+
+struct NoMck;
+
+/// Trait for master clock pins.
+pub trait PinMck<Block> {}
+impl PinMck<SAIA> for PE2<Alternate<AF6>> {}
+impl PinMck<SAIB> for PF7<Alternate<AF6>> {}
+impl<Block> PinMck<Block> for NoMck {}
+
+/// Trait for frame select pins.
+pub trait PinFs<Block> {}
+impl PinFs<SAIA> for PE4<Alternate<AF6>> {}
+impl PinFs<SAIB> for PF9<Alternate<AF6>> {}
+
+/// Trait for bit clock pins.
+pub trait PinSck<Block> {}
+impl PinSck<SAIA> for PE5<Alternate<AF6>> {}
+impl PinSck<SAIB> for PF8<Alternate<AF6>> {}
+
+/// Trait for data pins.
+pub trait PinSd<Block> {}
+impl PinSd<SAIA> for PD6<Alternate<AF6>> {}
+impl PinSd<SAIA> for PE6<Alternate<AF6>> {}
+impl PinSd<SAIB> for PE3<Alternate<AF6>> {}
+impl PinSd<SAIB> for PF6<Alternate<AF6>> {}
+
+/// Pins required for an asynchronous SAI master channel.
+pub trait MasterPins<Block> {}
+
+impl<Block, MCK, FS, SCK, SD> MasterPins<Block> for (MCK, FS, SCK, SD)
+where
+    MCK: PinMck<Block>,
+    FS: PinFs<Block>,
+    SCK: PinSck<Block>,
+    SD: PinSd<Block>,
+{
+}
+
+/// Pins required for an asynchronous SAI slave channel.
+pub trait SlavePins<Block> {}
+
+impl<Block, MCK, FS, SCK, SD> SlavePins<Block> for (MCK, FS, SCK, SD)
+where
+    MCK: PinMck<Block>,
+    FS: PinFs<Block>,
+    SCK: PinSck<Block>,
+    SD: PinSd<Block>,
+{
+}
+
+// TODO: SAIA is on Channel 0, Stream 1 and 3.
+// TODO: SAIB is on Channel 0, Stream 5 and Channel 1, Stream 4.
+
+/// Asynchronous SAI sub-block which has not yet been configured.
+///
+/// Asynchronous means that the sub-block has its own set of clock pins.
+pub struct Asynchronous;
+
+/// Asynchronous SAI sub-block which as been configured as a master.
+pub struct AsyncMaster<Pins> {
+    pins: Pins,
+}
+
+/// Asynchronous SAI sub-block which as been configured as a slave.
+pub struct AsyncSlave<Pins> {
+    pins: Pins,
+}
+
+/// Synchronous SAI sub-block.
+///
+/// Synchronous sub-blocks are always configured as slaves.
+pub struct Synchronous;
+
+/// SAI sub-block which has neither been configured as a receiver nor as a transmitter.
+pub struct NoDir;
+
+/// SAI sub-block which has been configured as a receiver.
+pub struct Receive;
+
+/// SAI sub-block which has been configured as a transmitter.
+pub struct Transmit;
+
+/// "A" channel of the SAI.
+pub struct SAIA;
+
+impl Deref for SAIA {
+    type Target = CH;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &(*SAI::ptr()).cha }
+    }
+}
+
+/// "B" channel of the SAI.
+pub struct SAIB;
+
+impl Deref for SAIB {
+    type Target = CH;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &(*SAI::ptr()).chb }
+    }
+}
+
+/// Wrapper for a single channel of the SAI and its configuration.
+pub struct SubBlock<Channel, Config, Direction> {
+    channel: Channel,
+    config: Config,
+    direction: Direction,
+}
+
+/// Functions to configure the two sub-blocks of an SAI instance.
+///
+/// For the two sub-blocks of a single SAI instance, only specific combinations of modes are valid.
+/// This trait has one method for each such combination.
+pub trait SAIExt {
+    /// Splits the SAI instance into two asynchronous sub-blocks.
+    fn split(
+        self,
+    ) -> (
+        SubBlock<SAIA, Asynchronous, NoDir>,
+        SubBlock<SAIB, Asynchronous, NoDir>,
+    )
+    where
+        Self: Sized;
+
+    /// Splits the SAI instance so that the A block uses the synchronization signals of the B
+    /// block.
+    fn split_sync_a(
+        self,
+    ) -> (
+        SubBlock<SAIA, Synchronous, NoDir>,
+        SubBlock<SAIB, Asynchronous, NoDir>,
+    )
+    where
+        Self: Sized;
+
+    /// Splits the SAI instance so that the B block uses the synchronization signals of the A
+    /// block.
+    fn split_sync_b(
+        self,
+    ) -> (
+        SubBlock<SAIA, Asynchronous, NoDir>,
+        SubBlock<SAIB, Synchronous, NoDir>,
+    )
+    where
+        Self: Sized;
+
+    /*/// Un-splits the two sub-blocks and resets the SAI.
+    fn uninit<ConfigA, ConfigB>(a: SubBlock<SAIA, ConfigA>, b: SubBlock<SAIB, ConfigB>) -> Self
+    where
+        Self: Sized;*/
+
+    /// Enables and resets the SAI instance.
+    fn reset(&mut self);
+}
+
+impl SAIExt for SAI {
+    fn split(
+        mut self,
+    ) -> (
+        SubBlock<SAIA, Asynchronous, NoDir>,
+        SubBlock<SAIB, Asynchronous, NoDir>,
+    )
+    where
+        Self: Sized,
+    {
+        self.reset();
+        (
+            SubBlock {
+                channel: SAIA,
+                config: Asynchronous,
+                direction: NoDir,
+            },
+            SubBlock {
+                channel: SAIB,
+                config: Asynchronous,
+                direction: NoDir,
+            },
+        )
+    }
+
+    fn split_sync_a(
+        mut self,
+    ) -> (
+        SubBlock<SAIA, Synchronous, NoDir>,
+        SubBlock<SAIB, Asynchronous, NoDir>,
+    )
+    where
+        Self: Sized,
+    {
+        self.reset();
+        (
+            SubBlock {
+                channel: SAIA,
+                config: Synchronous,
+                direction: NoDir,
+            },
+            SubBlock {
+                channel: SAIB,
+                config: Asynchronous,
+                direction: NoDir,
+            },
+        )
+    }
+
+    fn split_sync_b(
+        mut self,
+    ) -> (
+        SubBlock<SAIA, Asynchronous, NoDir>,
+        SubBlock<SAIB, Synchronous, NoDir>,
+    )
+    where
+        Self: Sized,
+    {
+        self.reset();
+        (
+            SubBlock {
+                channel: SAIA,
+                config: Asynchronous,
+                direction: NoDir,
+            },
+            SubBlock {
+                channel: SAIB,
+                config: Synchronous,
+                direction: NoDir,
+            },
+        )
+    }
+
+    /*fn uninit<ConfigA, ConfigB>(a: SubBlock<SAIA, ConfigA>, b: SubBlock<SAIB, ConfigB>) -> Self {
+        // TODO
+    }*/
+
+    fn reset(&mut self) {
+        let rcc = unsafe { &*RCC::ptr() };
+        rcc.apb2enr.modify(|_, w| w.sai1en().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.sai1rst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.sai1rst().clear_bit());
+    }
+}
+
+impl<Channel> SubBlock<Channel, Asynchronous, NoDir>
+where
+    Channel: Deref<Target = CH>,
+{
+    /// Configures the channel as a master and a receiver.
+    pub fn master_rx<Pins>(self, pins: Pins) -> SubBlock<Channel, AsyncMaster<Pins>, Receive>
+    where
+        Pins: MasterPins<Channel>,
+    {
+        // TODO: Clock/data type configuration?
+        SubBlock {
+            channel: self.channel,
+            config: AsyncMaster { pins },
+            direction: Receive,
+        }
+    }
+
+    /// Configures the channel as a master and a receiver.
+    pub fn master_tx<Pins>(self, pins: Pins) -> SubBlock<Channel, AsyncMaster<Pins>, Transmit>
+    where
+        Pins: MasterPins<Channel>,
+    {
+        // TODO: Clock/data type configuration?
+        SubBlock {
+            channel: self.channel,
+            config: AsyncMaster { pins },
+            direction: Transmit,
+        }
+    }
+
+    /// Configures the channel as a slave and a receiver.
+    pub fn slave_rx<Pins>(self, pins: Pins) -> SubBlock<Channel, AsyncSlave<Pins>, Receive>
+    where
+        Pins: SlavePins<Channel>,
+    {
+        // TODO: Data type configuration?
+        SubBlock {
+            channel: self.channel,
+            config: AsyncSlave { pins },
+            direction: Receive,
+        }
+    }
+
+    /// Configures the channel as a master and a receiver.
+    pub fn slave_tx<Pins>(self, pins: Pins) -> SubBlock<Channel, AsyncSlave<Pins>, Transmit>
+    where
+        Pins: SlavePins<Channel>,
+    {
+        // TODO: Data type configuration?
+        SubBlock {
+            channel: self.channel,
+            config: AsyncSlave { pins },
+            direction: Transmit,
+        }
+    }
+}
+
+impl<Channel, Config> SubBlock<Channel, Config, Receive>
+where
+    Channel: Deref<Target = CH>,
+{
+    // TODO
+}
+
+impl<Channel, Config> SubBlock<Channel, Config, Transmit>
+where
+    Channel: Deref<Target = CH>,
+{
+    // TODO
+}
+
+/// Wrapper around `Receive` and `Transmit` blocks to provide full-duplex I2S transfers.
+pub struct Duplex<Channel1, Config1, Channel2, Config2> {
+    rx: SubBlock<Channel1, Config1, Receive>,
+    tx: SubBlock<Channel2, Config2, Transmit>,
+}
+
+impl<Channel1, Config1, Channel2, Config2> Duplex<Channel1, Config1, Channel2, Config2>
+where
+    Channel1: Deref<Target = CH>,
+    Channel2: Deref<Target = CH>,
+{
+    /// Wraps the specified receiver/transmitter objects.
+    pub fn new(
+        rx: SubBlock<Channel1, Config1, Receive>,
+        tx: SubBlock<Channel2, Config2, Transmit>,
+    ) -> Self {
+        // TODO
+        Self { rx, tx }
+    }
+
+    pub fn try_read(&mut self) -> nb::Result<(u32, u32), Self::Error> {
+        // TODO
+    }
+
+    pub fn try_send(&mut self) -> nb::Result<(u32, u32), Self::Error> {
+        // TODO
+    }
+}
+
+/*impl<
+        SAIX: SAIExt<SAIX>,
+        RxBlockInner: SubBlock<SAI = SAIX>,
+        RxBlock: SubBlockConfig<SubBlock = RxBlockInner>,
+        TxBlockInner: SubBlock<SAI = SAIX>,
+        TxBlock: SubBlockConfig<SubBlock = TxBlockInner>,
+    > Duplex<SAIX, RxBlockInner, RxBlock, TxBlockInner, TxBlock>
+{
+    /// Wraps the specified receiver/transmitter objects.
+    pub fn new(rx: Receive<RxBlock>, tx: Transmit<TxBlock>) -> Self {
+        // TODO
+        Self {
+            rx,
+            tx,
+            _rx_inner: PhantomData,
+            _tx_inner: PhantomData,
+        }
+    }
+
+    /// Starts transmitting and receiving data.
+    ///
+    /// For I2S masters, this function starts the clock signals.
+    pub fn start(&mut self) {
+        // TODO
+    }
+
+    /// Stops transmitting and receiving data.
+    pub fn stop(&mut self) {
+        // TODO
+    }
+}*/
+
+/*// Use cases:
+// - SAI should be usable as two simplex I2S interfaces, both either slave or master.
+// - SAI should be usable as one duplex I2S interface, either as slave or master.
+// - SAI should be usable as two simple I2S interfaces with synchronization
+
+/// Mode of an SAI sub-block (sync/async, master/slave).
+pub trait SubBlockConfig {
+    type SubBlock: SubBlock;
+    // TODO
+}
+
+/// SAI block configured to use the synchronization signals of its asynchronous sibling block.
+pub struct Synchronous<Block> {
+    block: Block,
+}
+
+impl<Block> Synchronous<Block>
+where
+    Block: SubBlock,
+{
+    /// Configures this sub-block as a slave.
+    pub fn slave<SDPin: SD<Block>>(mut self, sd: SDPin) -> SyncSlave<Block, SDPin> {
+        self.block.set_slave();
+        SyncSlave {
+            block: self.block,
+            sd,
+        }
+    }
+}
+
+/// SAI sub-block configured as a synchronous slave.
+pub struct SyncSlave<Block, SDPin> {
+    block: Block,
+    sd: SDPin,
+    // TODO
+}
+
+impl<Block, SDPin> SyncSlave<Block, SDPin> {
+    /// Uninitializes the sub-block, releasing the pins.
+    pub fn destroy(self) -> (Asynchronous<Block>, SDPin) {
+        // TODO: Disable?
+        (Asynchronous { block: self.block }, self.sd)
+    }
+}
+
+impl<Block, SDPin> SubBlockConfig for SyncSlave<Block, SDPin>
+where
+    Block: SubBlock,
+{
+    type SubBlock = Block;
+    // TODO
+}
+
+/// SAI block configured to provide its own synchronization signals (either as inputs in the case
+/// o a slave or via a clock generator in the case of a master).
+pub struct Asynchronous<Block> {
+    block: Block,
+}
+
+impl<Block> Asynchronous<Block>
+where
+    Block: SubBlock,
+{
+    /// Configures this sub-block as a master.
+    pub fn master<MCKPin, FSPin, SCKPin, SDPin>(
+        mut self,
+        mck: MCKPin,
+        fs: FSPin,
+        sck: SCKPin,
+        sd: SDPin,
+        _clocks: I2SClocks,
+    ) -> AsyncMaster<Block, MCKPin, FSPin, SCKPin, SDPin>
+    where
+        MCKPin: MCK<Block>,
+        FSPin: FS<Block>,
+        SCKPin: SCK<Block>,
+        SDPin: SD<Block>,
+    {
+        self.block.set_master();
+        AsyncMaster {
+            block: self.block,
+            mck,
+            fs,
+            sck,
+            sd,
+        }
+    }
+
+    /// Configures this sub-block as a slave.
+    pub fn slave<FSPin, SCKPin, SDPin>(
+        mut self,
+        fs: FSPin,
+        sck: SCKPin,
+        sd: SDPin,
+    ) -> AsyncSlave<Block, FSPin, SCKPin, SDPin>
+    where
+        FSPin: FS<Block>,
+        SCKPin: SCK<Block>,
+        SDPin: SD<Block>,
+    {
+        self.block.set_slave();
+        AsyncSlave {
+            block: self.block,
+            fs,
+            sck,
+            sd,
+        }
+    }
+}
+
+/// SAI sub-block configured as a master.
+pub struct AsyncMaster<Block, MCKPin, FSPin, SCKPin, SDPin> {
+    block: Block,
+    mck: MCKPin,
+    fs: FSPin,
+    sck: SCKPin,
+    sd: SDPin,
+}
+
+impl<Block, MCKPin, FSPin, SCKPin, SDPin> AsyncMaster<Block, MCKPin, FSPin, SCKPin, SDPin> {
+    /// Uninitializes the sub-block, releasing the pins.
+    pub fn destroy(self) -> (Asynchronous<Block>, MCKPin, FSPin, SCKPin, SDPin) {
+        // TODO: Disable?
+        (
+            Asynchronous { block: self.block },
+            self.mck,
+            self.fs,
+            self.sck,
+            self.sd,
+        )
+    }
+}
+
+impl<Block, MCKPin, FSPin, SCKPin, SDPin> SubBlockConfig
+    for AsyncMaster<Block, MCKPin, FSPin, SCKPin, SDPin>
+where
+    Block: SubBlock,
+{
+    type SubBlock = Block;
+    // TODO
+}
+
+/// SAI sub-block configured as an asynchronous slave.
+pub struct AsyncSlave<Block, FSPin, SCKPin, SDPin> {
+    block: Block,
+    fs: FSPin,
+    sck: SCKPin,
+    sd: SDPin,
+}
+
+impl<Block, FSPin, SCKPin, SDPin> AsyncSlave<Block, FSPin, SCKPin, SDPin> {
+    /// Uninitializes the sub-block, releasing the pins.
+    pub fn destroy(self) -> (Asynchronous<Block>, FSPin, SCKPin, SDPin) {
+        // TODO: Disable?
+        (
+            Asynchronous { block: self.block },
+            self.fs,
+            self.sck,
+            self.sd,
+        )
+    }
+}
+
+impl<Block, FSPin, SCKPin, SDPin> SubBlockConfig for AsyncSlave<Block, FSPin, SCKPin, SDPin>
+where
+    Block: SubBlock,
+{
+    type SubBlock = Block;
+    // TODO
+}
+
+/// SAI sub-block configured as a transmitter.
+pub struct Transmit<Block: SubBlockConfig> {
+    block: Block,
+}
+
+impl<Block: SubBlockConfig> Transmit<Block> {
+    /// Initializes the sub-block as a transmitter.
+    pub fn new(block: Block) -> Self {
+        // TODO: Configuration.
+        Self { block }
+    }
+
+    /// Starts transmitting data.
+    ///
+    /// For I2S masters, this function starts the clock signals.
+    pub fn start(&mut self) {
+        // TODO
+    }
+
+    /// Stops transmitting data.
+    pub fn stop(&mut self) {
+        // TODO
+    }
+}
+
+/// SAI sub-block configured as a receiver.
+pub struct Receive<Block: SubBlockConfig> {
+    block: Block,
+}
+
+impl<Block: SubBlockConfig> Receive<Block> {
+    /// Initializes the sub-block as a receiver.
+    pub fn new(block: Block) -> Self {
+        // TODO: Configuration.
+        Self { block }
+    }
+
+    /// Starts receiving data.
+    ///
+    /// For I2S masters, this function starts the clock signals.
+    pub fn start(&mut self) {
+        // TODO
+    }
+
+    /// Stops receiving data.
+    pub fn stop(&mut self) {
+        // TODO
+    }
+}*/