firmware: I2S test.

hackamp/firmware/Cargo.lock

@@ -125,6 +125,15 @@ dependencies = [
  "cortex-m",
 ]
 
+[[package]]
+name = "embedded-dma"
+version = "0.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "46c8c02e4347a0267ca60813c952017f4c5948c232474c6010a381a337f1bda4"
+dependencies = [
+ "stable_deref_trait",
+]
+
 [[package]]
 name = "embedded-hal"
 version = "0.2.4"
@@ -328,13 +337,12 @@ dependencies = [
 [[package]]
 name = "stm32f4xx-hal"
 version = "0.8.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b3a2f044469d1e3aff2cd02bee8b2724f3d5d91f3175e5d1ec99770320d16192"
 dependencies = [
  "bare-metal",
  "cast",
  "cortex-m",
  "cortex-m-rt",
+ "embedded-dma",
  "embedded-hal",
  "nb 0.1.3",
  "rand_core",
@@ -343,16 +351,6 @@ dependencies = [
  "void",
 ]
 
-[[package]]
-name = "stm32ral"
-version = "0.3.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8665561cb3422ddf54d257bf6cb3c5432ba0684f6937c4ad987bad16aa6ca496"
-dependencies = [
- "bare-metal",
- "cortex-m",
-]
-
 [[package]]
 name = "syn"
 version = "1.0.48"
@@ -366,12 +364,11 @@ dependencies = [
 
 [[package]]
 name = "synopsys-usb-otg"
-version = "0.1.0"
+version = "0.2.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6bcd2ca4e946cd2f33dfe2b0485f6b3c306721a035699f44f576d69e45b38db0"
+checksum = "461676dcf123675b3d3b02e2390e6a690cd186aacf2f439af7673c79e2561d53"
 dependencies = [
  "cortex-m",
- "stm32ral",
  "usb-device",
  "vcell",
 ]

hackamp/firmware/Cargo.toml

@@ -8,9 +8,11 @@ edition = "2018"
 cortex-m = "0.6"
 cortex-m-rt = "0.6"
 cortex-m-rtic = "0.5.3"
+#cortex-m-semihosting = "0.3.5"
 embedded-hal = "0.2.3"
 panic-semihosting = "0.5"
-stm32f4xx-hal = { version = "0.8.3", features = ["stm32f429", "usb_hs"] }
+#stm32f4xx-hal = { git = "https://github.com/stm32-rs/stm32f4xx-hal.git", features = ["stm32f429", "usb_hs"] }
+stm32f4xx-hal = { path = "/home/mathias/Projects/microcontroller/stm32-usb-audio/stm32f4xx-hal", features = ["stm32f429", "usb_hs"] }
 
 [profile]
 [profile.release]

hackamp/firmware/src/audio_buffer.rs

@@ -74,7 +74,7 @@ impl AudioBuffer {
     pub fn borrow_read(&'static self, cs: &CriticalSection) -> Option<ReadPacket> {
         let inner = self.mutex.borrow(cs);
         let valid = inner.valid.get();
-        if valid != 0 {
+        if valid == 0 {
             return None;
         }
         let index = valid.trailing_zeros();
@@ -110,7 +110,7 @@ impl AudioBuffer {
     pub fn borrow_write(&'static self, cs: &CriticalSection) -> Option<WritePacket> {
         let inner = self.mutex.borrow(cs);
         let invalid = inner.invalid.get();
-        if invalid != 0 {
+        if invalid == 0 {
             return None;
         }
         let index = invalid.trailing_zeros();

hackamp/firmware/src/halext/i2s.rs

@@ -0,0 +1,232 @@
+//! I2S interface with DMA data transfer.
+
+use cortex_m::interrupt;
+use stm32f4xx_hal::dma;
+use stm32f4xx_hal::dma::traits::Stream;
+use stm32f4xx_hal::gpio::gpiob::{PB12, PB13, PB14, PB15};
+use stm32f4xx_hal::gpio::gpioc::PC6;
+use stm32f4xx_hal::gpio::{Alternate, AF5, AF6};
+use stm32f4xx_hal::stm32::{DMA1, I2S2EXT, RCC, SPI2};
+
+use crate::audio_buffer::{AudioBuffer, ReadPacket, WritePacket, CHANNELS, SAMPLES_PER_PACKET};
+
+/// Clocks for the I2S peripheral.
+#[derive(Clone, Copy)]
+pub struct I2SClocks {
+    plli2sclk: u32,
+}
+
+impl I2SClocks {
+    /// Initializes the I2S clocks.
+    ///
+    /// This function must only be called once at startup. It assumes that the HSE is already
+    /// initialized and the HSE frequency is 8MHz.
+    pub unsafe fn init() -> I2SClocks {
+        // The following values result in a sample frequency of 47991.07Hz:
+        // - PLLI2SN = 43
+        // - PLLI2SR = 4
+        // - I2SDIV = 3
+        // - I2SODD = 1
+
+        let rcc = &*RCC::ptr();
+        // Configure PLL.
+        rcc.plli2scfgr
+            .modify(|_, w| w.plli2sn().bits(43).plli2sq().bits(4).plli2sr().bits(4));
+        // Enable PLL.
+        rcc.cr.modify(|_, w| w.plli2son().set_bit());
+        // Wait for PLL to stabilise
+        while rcc.cr.read().plli2srdy().bit_is_clear() {}
+
+        // Ensure that the PLL is selected as the I2S clock source.
+        rcc.cfgr.modify(|_, w| w.i2ssrc().clear_bit());
+
+        I2SClocks {
+            plli2sclk: 86000000,
+        }
+    }
+}
+
+/// I2S interface with DMA data transfer.
+pub struct I2S {
+    spi: SPI2,
+    i2sext: I2S2EXT,
+    rx_dma: dma::Stream3<DMA1>,
+    tx_dma: dma::Stream4<DMA1>,
+    in_: &'static AudioBuffer,
+    in_packets: [Option<WritePacket>; 2],
+    out: &'static AudioBuffer,
+    out_packets: [Option<ReadPacket>; 2],
+}
+
+impl I2S {
+    /// Initializes the I2S interface to read from/write to the specified buffers.
+    ///
+    /// The interface is only started when the `start()` function is called.
+    pub fn new(
+        spi: SPI2,
+        i2sext: I2S2EXT,
+        mut rx_dma: dma::Stream3<DMA1>,
+        mut tx_dma: dma::Stream4<DMA1>,
+        mck: PC6<Alternate<AF5>>,
+        ws: PB12<Alternate<AF5>>,
+        ck: PB13<Alternate<AF5>>,
+        sdin: PB14<Alternate<AF6>>,
+        sdout: PB15<Alternate<AF5>>,
+        in_: &'static AudioBuffer,
+        out: &'static AudioBuffer,
+        _clocks: I2SClocks,
+    ) -> I2S {
+        // Enable and reset the peripheral.
+        let rcc = unsafe { &*RCC::ptr() };
+        rcc.apb1enr.modify(|_, w| w.spi2en().set_bit());
+        rcc.apb1rstr.modify(|_, w| w.spi2rst().set_bit());
+        rcc.apb1rstr.modify(|_, w| w.spi2rst().clear_bit());
+        //rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit());
+
+        // Disable SS output.
+        spi.cr2.write(|w| w.ssoe().clear_bit());
+
+        // Configure the pins.
+        // TODO
+
+        // Configure the clocks.
+        // For the values, see the comment in I2SClocks::init().
+        spi.i2spr
+            .write(|w| unsafe { w.mckoe().set_bit().odd().set_bit().i2sdiv().bits(3) });
+        i2sext
+            .i2spr
+            .write(|w| unsafe { w.mckoe().set_bit().odd().set_bit().i2sdiv().bits(3) });
+
+        // Configure I2S.
+        spi.i2scfgr.modify(|_, w| unsafe {
+            w.i2smod()
+                .set_bit()
+                .i2se()
+                .clear_bit()
+                .i2scfg()
+                .master_tx()
+                .i2sstd()
+                .bits(0b01)
+                .ckpol()
+                .idle_high()
+                .datlen()
+                .bits(0b10)
+                .chlen()
+                .set_bit()
+        });
+        i2sext.i2scfgr.modify(|_, w| unsafe {
+            w.i2smod()
+                .set_bit()
+                .i2se()
+                .clear_bit()
+                .i2scfg()
+                .slave_rx()
+                .i2sstd()
+                .bits(0b01)
+                .ckpol()
+                .idle_high()
+                .datlen()
+                .bits(0b10)
+                .chlen()
+                .set_bit()
+        });
+        i2sext.cr2.modify(|_, w| w.rxdmaen().set_bit());
+        spi.cr2.modify(|_, w| w.txdmaen().set_bit());
+
+        rx_dma.set_channel(dma::Channel3);
+        rx_dma.clear_interrupts();
+        unsafe {
+            rx_dma.set_memory_size(1);
+            rx_dma.set_peripheral_size(1);
+        }
+        rx_dma.set_memory_increment(true);
+        rx_dma.set_direction(dma::PeripheralToMemory);
+        rx_dma.set_interrupts_enable(true, false, true, true);
+        rx_dma.set_double_buffer(true);
+        rx_dma.set_fifo_enable(false);
+        rx_dma.set_number_of_transfers((SAMPLES_PER_PACKET * CHANNELS * 2) as u16);
+
+        tx_dma.set_channel(dma::Channel0);
+        tx_dma.clear_interrupts();
+        unsafe {
+            tx_dma.set_memory_size(1);
+            tx_dma.set_peripheral_size(1);
+        }
+        tx_dma.set_memory_increment(true);
+        tx_dma.set_direction(dma::MemoryToPeripheral);
+        tx_dma.set_interrupts_enable(true, false, true, true);
+        tx_dma.set_double_buffer(true);
+        tx_dma.set_fifo_enable(false);
+        tx_dma.set_number_of_transfers((SAMPLES_PER_PACKET * CHANNELS * 2) as u16);
+
+        const DR_OFFSET: usize = 0x0c;
+        let spi_dr = SPI2::ptr() as usize + DR_OFFSET;
+        let i2sext_dr = I2S2EXT::ptr() as usize + DR_OFFSET;
+        rx_dma.set_peripheral_address(i2sext_dr as u32);
+        tx_dma.set_peripheral_address(spi_dr as u32);
+
+        I2S {
+            spi,
+            i2sext,
+            rx_dma,
+            tx_dma,
+            in_,
+            in_packets: [None, None],
+            out,
+            out_packets: [None, None],
+        }
+    }
+
+    /// Starts the data stream of the I2S interface.
+    pub fn start(&mut self) {
+        interrupt::free(|cs| {
+            for i in 0..2 {
+                self.in_packets[i] = self.in_.borrow_write(cs);
+            }
+            for i in 0..2 {
+                self.out_packets[i] = self.out.borrow_read(cs);
+            }
+        });
+
+        // The system was just started, and some buffers were filled with dummy data, so we can
+        // assume that borrowing was successful.
+        let in_0 = self.in_packets[0].as_mut().unwrap().as_mut().as_ptr() as usize as u32;
+        let in_1 = self.in_packets[1].as_mut().unwrap().as_mut().as_ptr() as usize as u32;
+        self.rx_dma.set_memory_address(in_0);
+        self.rx_dma.set_memory_double_buffer_address(in_1);
+        /*self.dma.st[3].m0ar.write(|w| unsafe { w.bits(in_0) });
+        self.dma.st[3].m1ar.write(|w| unsafe { w.bits(in_1) });*/
+        let out_0 = self.out_packets[0].as_ref().unwrap().as_ref().as_ptr() as usize as u32;
+        let out_1 = self.out_packets[1].as_ref().unwrap().as_ref().as_ptr() as usize as u32;
+        self.tx_dma.set_memory_address(out_0);
+        self.tx_dma.set_memory_double_buffer_address(out_1);
+        /*self.dma.st[4].m0ar.write(|w| unsafe { w.bits(out_0) });
+        self.dma.st[4].m1ar.write(|w| unsafe { w.bits(out_1) });*/
+
+        // Enable DMA and activate the I2S peripherals.
+        /*self.dma.st[3].cr.modify(|_, w| w.en().set_bit());
+        self.dma.st[4].cr.modify(|_, w| w.en().set_bit());*/
+        unsafe {
+            self.rx_dma.enable();
+            self.tx_dma.enable();
+        }
+        self.i2sext.i2scfgr.modify(|_, w| w.i2se().set_bit());
+        self.spi.i2scfgr.modify(|_, w| w.i2se().set_bit());
+
+        /*loop {
+            if self.spi.sr.read().txe().bit_is_set() {
+                self.spi.dr.write(|w| unsafe { w.bits(0xaaaa) });
+            }
+            if self.i2sext.sr.read().rxne().bit_is_set() {
+                self.i2sext.dr.read();
+            }
+        }*/
+    }
+
+    /// Reads data from the output audio buffer and writes to the input audio buffer as required.
+    ///
+    /// This function needs to be called from the DMA interrupt handler.
+    pub fn poll(&mut self) {
+        // TODO
+    }
+}

hackamp/firmware/src/halext/mod.rs

@@ -1,2 +1,4 @@
 //! Hardware drivers missing in the HAL.
 #![warn(missing_docs)]
+
+pub mod i2s;

hackamp/firmware/src/main.rs

@@ -4,8 +4,11 @@
 
 use cortex_m::interrupt;
 use panic_semihosting as _;
+use stm32f4xx_hal::dma::StreamsTuple;
+use stm32f4xx_hal::prelude::*;
 
 use audio_buffer::AudioBuffer;
+use halext::i2s::{I2SClocks, I2S};
 use pins::Pins;
 
 // Remove "pub" to check whether there is any dead code.
@@ -19,27 +22,77 @@ const APP: () = {
     struct Resources {}
 
     #[init]
-    fn init(_ctx: init::Context) {
+    fn init(ctx: init::Context) {
+        // Initialize clocks.
+        let rcc = ctx.device.RCC.constrain();
+        let _clocks = rcc
+            .cfgr
+            .use_hse(8.mhz())
+            .sysclk(48.mhz())
+            .pclk1(24.mhz())
+            .require_pll48clk()
+            .freeze();
+        let i2sclocks = unsafe { I2SClocks::init() };
+
+        // Configure the GPIOs.
+        let gpiob = ctx.device.GPIOB.split();
+        let gpioc = ctx.device.GPIOC.split();
         let _pins = Pins::configure();
-        static I2S_BUFFER: AudioBuffer = AudioBuffer::new();
 
-        let i2s_buffer = &I2S_BUFFER;
+        // The components of the firmware are connected via audio buffers.
+        static AMP_I2S_IN_BUFFER: AudioBuffer = AudioBuffer::new();
+        static AMP_I2S_OUT_BUFFER: AudioBuffer = AudioBuffer::new();
+        //static BT_I2S_IN_BUFFER: AudioBuffer = AudioBuffer::new();
+        static BT_I2S_OUT_BUFFER: AudioBuffer = AudioBuffer::new();
+        /*static USB1_IN_BUFFER: AudioBuffer = AudioBuffer::new();
+        static USB1_OUT_BUFFER: AudioBuffer = AudioBuffer::new();
+        static USB2_IN_BUFFER: AudioBuffer = AudioBuffer::new();
+        static USB2_OUT_BUFFER: AudioBuffer = AudioBuffer::new();*/
 
-        // Buffer example code.
+        // We initialize the output audio buffers with some data. As the I2S input buffers are
+        // filled at the same rate as the I2S output buffers, this initial state ensures that the
+        // output buffers never run empty (note that the USB audio interfaces perform their own
+        // adaptive synchronization).
         interrupt::free(|cs| {
-            let write_packet = i2s_buffer.borrow_write(cs).unwrap();
-            // TODO
-            i2s_buffer.write_finished(write_packet, cs);
-            let read_packet = i2s_buffer.borrow_read(cs).unwrap();
-            // TODO
-            i2s_buffer.read_finished(read_packet, cs);
+            for buffer in [&AMP_I2S_OUT_BUFFER, &BT_I2S_OUT_BUFFER].iter() {
+                // We initialize two packets so that the I2S interface can immediately initialize
+                // both DMA buffers (double buffering).
+                for _ in 0..2 {
+                    let mut packet = buffer.borrow_write(cs).unwrap();
+                    let data = packet.as_mut();
+                    for i in 0..data.len() {
+                        data[i] = 0x8000000; // "0"
+                    }
+                    buffer.write_finished(packet, cs);
+                }
+            }
         });
+
+        let dma = StreamsTuple::new(ctx.device.DMA1);
+        let mut i2s = I2S::new(
+            ctx.device.SPI2,
+            ctx.device.I2S2EXT,
+            dma.3,
+            dma.4,
+            gpioc.pc6.into_alternate_af5(),
+            gpiob.pb12.into_alternate_af5(),
+            gpiob.pb13.into_alternate_af5(),
+            gpiob.pb14.into_alternate_af6(),
+            gpiob.pb15.into_alternate_af5(),
+            &AMP_I2S_IN_BUFFER,
+            &AMP_I2S_OUT_BUFFER,
+            i2sclocks,
+        );
+
+        i2s.start();
+
+        // TODO: Resources.
     }
 
-    #[idle(resources = [])]
+    /*#[idle(resources = [])]
     fn idle(_ctx: idle::Context) -> ! {
         loop {
             // TODO
         }
-    }
+    }*/
 };