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nrf24l01.c 10KB

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  1. #include <stdint.h>
  2. #include <avr/io.h>
  3. #include <util/delay.h>
  4. #include <stdio.h>
  5. #include <stdbool.h>
  6. #include "led.h" // TODO: for debugging
  7. #include "spi.h"
  8. #include "nrf24l01.h"
  9. #include "nrf24l01_definitions.h"
  10. /* TODO
  11. * - Send functions
  12. * - Interrupt handling for Send
  13. */
  14. extern volatile bool nrfInterruptRaised;
  15. void Print_Register_Contents(uint8_t address);
  16. void Send_TX_Flush_Command(void);
  17. void Send_RX_Flush_Command(void);
  18. static uint8_t Write_One_Byte(uint8_t byte1);
  19. static uint8_t Write_Two_Bytes(uint8_t byte1, uint8_t byte2);
  20. static void Write_Byte_And_Buffer(uint8_t byte, uint8_t * buffer, uint8_t length);
  21. /* Startup and initial configuration of the NRF24L01 */
  22. void Initialize_NRF24L01(void)
  23. {
  24. CONFIG_REGISTER configRegisterContents = {.byte = 0x0};
  25. /* Configure the AVR pins for the nrf24l01 */
  26. Set_NRF24L01_Pins();
  27. /* Wait more than 10.3 ms to make sure the nrf24l01 is running */
  28. _delay_ms(11);
  29. /* Write the PWR_UP bit of the CONFIG register (EN_CRC is also set) */
  30. configRegisterContents.bits.EN_CRC = 0x1;
  31. configRegisterContents.bits.PWR_UP = 0x1;
  32. Write_NRF_Register(CONFIG_ADDRESS, configRegisterContents.byte);
  33. /* Wait more than 1.5 ms for the change to take effect */
  34. _delay_ms(2);
  35. /* The NRF24L01 is now in the mode Standby-I */
  36. }
  37. void Set_NRF24L01_Pins(void)
  38. {
  39. /* Set up the NRF24L01 */
  40. NRF_CE_DDR |= (1 << NRF_CE_PIN);
  41. NRF_CSN_DDR |= (1 << NRF_CSN_PIN);
  42. /* Set the chip select pin to not selected */
  43. NRF_CSN_PORT |= (1 << NRF_CSN_PIN);
  44. /* Ensure that the CE pin is set to 0*/
  45. NRF_CE_PORT &= ~(1 << NRF_CE_PIN);
  46. /* Set the interrupt pin */
  47. /* TODO: PCINT21 -> PCINT2 */
  48. NRF_IRQ_DDR &= ~(1 << NRF_IRQ_PIN); // Set the pin as input
  49. NRF_IRQ_PORT |= (1 << NRF_IRQ_PORT); // Enable the pullup for the pin
  50. }
  51. void Configure_Transmission(uint8_t moduleId)
  52. {
  53. SETUP_RETR_REGISTER setupRetrRegisterContents = {.byte = 0x0};
  54. EN_RXADDR_REGISTER enableRxAddressesRegisterContents = {.byte = 0x0};
  55. RX_PW_Pn_REGISTER rxPwPnRegisterContents = {.byte = 0x0};
  56. EN_AA_REGISTER enAaRegister = {.byte = 0x0};
  57. FEATURE_REGISTER featureRegisterContents = {.byte = 0x0};
  58. DYNPD_REGISTER dyndpRegisterContents = {.byte = 0x0};
  59. uint8_t txAddress[5] = {0xB3, 0xB3, 0xB3, 0xB3, 0x00};
  60. uint8_t rx1Address[5] = {0xB3, 0xB3, 0xB3, 0xB3, 0x00};
  61. /* Set the frequency to 1450 MHz */
  62. Write_NRF_Register(RF_CH_ADDRESS, 0x32);
  63. /* Enable dynamic payload length */
  64. Send_Activate_Command();
  65. featureRegisterContents.bits.EN_DPL = 1; // enable dynamic payload length
  66. Write_NRF_Register(FEATURE_ADDRESS, featureRegisterContents.byte);
  67. /* set dynamic payload length for all data pipes
  68. * When the dynamic payload length is not set the module cannot receive packets from some
  69. * stations. This is probably due to counterfeit NRF24L01+ chips.
  70. */
  71. dyndpRegisterContents.bits.DPL_P0 = 1;
  72. dyndpRegisterContents.bits.DPL_P1 = 1;
  73. dyndpRegisterContents.bits.DPL_P2 = 1;
  74. dyndpRegisterContents.bits.DPL_P3 = 1;
  75. dyndpRegisterContents.bits.DPL_P4 = 1;
  76. dyndpRegisterContents.bits.DPL_P5 = 1;
  77. Write_NRF_Register(DYNPD_ADDRESS, dyndpRegisterContents.byte);
  78. /* Set up the auto retries */
  79. setupRetrRegisterContents.bits.ARC = 0x3;
  80. setupRetrRegisterContents.bits.ARD = 0xF;
  81. Write_NRF_Register(SETUP_RETR_ADDRESS, setupRetrRegisterContents.byte);
  82. /* Set the TX address */
  83. Set_TX_Address(txAddress, MAX_ADDRESS_LENGTH);
  84. /* Set the address of the RX pipe 0 to the one of the base station to receive acks */
  85. Set_RX_P0_Address(txAddress, MAX_ADDRESS_LENGTH);
  86. /* Set the address of the RX pipe 1 to the own address to receive messages */
  87. rx1Address[4] = moduleId; // The last byte of the address corresponds to the Id set by the pin programming
  88. Set_RX_P1_Address(rx1Address, MAX_ADDRESS_LENGTH);
  89. /* Enable the rx addresses for pipe 0 and pipe 1*/
  90. enableRxAddressesRegisterContents.bits.ERX_P0 = 1;
  91. enableRxAddressesRegisterContents.bits.ERX_P1 = 1;
  92. Write_NRF_Register(EN_RXADDR_ADDRESS, enableRxAddressesRegisterContents.byte);
  93. /* Set the payload witth for pipe 1 */
  94. rxPwPnRegisterContents.bits.RX_PW_Pn = 32;
  95. Write_NRF_Register(RX_PW_P1_ADDRESS, rxPwPnRegisterContents.byte);
  96. rxPwPnRegisterContents.bits.RX_PW_Pn = 0;
  97. Write_NRF_Register(RX_PW_P0_ADDRESS, rxPwPnRegisterContents.byte); // auto-ack pipe
  98. Write_NRF_Register(RX_PW_P2_ADDRESS, rxPwPnRegisterContents.byte); // not used
  99. Write_NRF_Register(RX_PW_P3_ADDRESS, rxPwPnRegisterContents.byte); // not used
  100. Write_NRF_Register(RX_PW_P4_ADDRESS, rxPwPnRegisterContents.byte); // not used
  101. Write_NRF_Register(RX_PW_P5_ADDRESS, rxPwPnRegisterContents.byte); // not used
  102. /* Enable auto acknowledge for pipe 1 */
  103. enAaRegister.bits.ENAA_P0 = 1;
  104. enAaRegister.bits.ENAA_P1 = 1;
  105. enAaRegister.bits.ENAA_P2 = 1;
  106. enAaRegister.bits.ENAA_P3 = 1;
  107. enAaRegister.bits.ENAA_P4 = 1;
  108. enAaRegister.bits.ENAA_P5 = 1;
  109. Write_NRF_Register(EN_AA_ADDRESS, enAaRegister.byte);
  110. /* Flush FIFOs */
  111. Send_TX_Flush_Command();
  112. Send_RX_Flush_Command();
  113. PCMSK2 |= (1<<PCINT21); // Set the external interrupt for PD5
  114. }
  115. bool NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
  116. {
  117. bool success = false;
  118. STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
  119. if ((length > 32) || (length == 0))
  120. {
  121. return success;
  122. }
  123. PCICR |= (1<<PCIE2); // Enable the interrupt for the IRQ signal
  124. Write_Message_To_TX_FIFO(length, buffer);
  125. /* Set CE = 1 for more than 10 us */
  126. NRF_CE_PORT |= (1 << NRF_CE_PIN);
  127. _delay_us(15);
  128. NRF_CE_PORT &= ~(1 << NRF_CE_PIN);
  129. while (nrfInterruptRaised == false); // Wait until the transmission is complete
  130. /* An interrupt instead of polling the status register is used to avoid transmission errors
  131. * induced by the SPI:
  132. * https://forum.mysensors.org/topic/10452/nrf24l01-communication-failure-root-cause-and-solution
  133. */
  134. statusRegisterContents.byte = Read_NRF_Status_Register();
  135. if (statusRegisterContents.bits.MAX_RT == 1)
  136. {
  137. Send_TX_Flush_Command(); /* Remove the packet from the TX FIFO as it is not done automatically */
  138. }
  139. else
  140. {
  141. success = true;
  142. }
  143. /* Reset the interrupts */
  144. statusRegisterContents.bits.TX_DS = 1;
  145. statusRegisterContents.bits.MAX_RT = 1;
  146. statusRegisterContents.bits.RX_DR = 1;
  147. Write_NRF_Register(STATUS_ADDRESS, statusRegisterContents.byte);
  148. PCICR &= ~(1<<PCIE2); // Disable the interrupt for the IRQ signal
  149. nrfInterruptRaised = false;
  150. return success;
  151. }
  152. bool NRF24L01_Receive_Message(uint8_t *buffer, uint8_t duration)
  153. {
  154. uint8_t messageReceived = false;
  155. CONFIG_REGISTER configRegisterContents = {.byte = 0x0};
  156. STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
  157. FIFO_STATUS_REGISTER fifoStatusRegisterContents = {.byte = 0x0};
  158. PCICR |= (1<<PCIE2); // Enable the interrupt for the IRQ signal
  159. // Enable the receive mode
  160. configRegisterContents.byte = Read_NRF_Register(CONFIG_ADDRESS);
  161. configRegisterContents.bits.PRIM_RX = 0x1;
  162. Write_NRF_Register(CONFIG_ADDRESS, configRegisterContents.byte);
  163. NRF_CE_PORT |= (1 << NRF_CE_PIN);
  164. _delay_ms(10);
  165. while ((nrfInterruptRaised == false) && (duration > 0))
  166. {
  167. _delay_ms(1);
  168. duration --;
  169. };
  170. if (nrfInterruptRaised == true) // check if a message was received
  171. {
  172. /* A message was received */
  173. statusRegisterContents.byte = Read_NRF_Status_Register();
  174. fifoStatusRegisterContents.byte = Read_NRF_Register(FIFO_STATUS_ADDRESS);
  175. if (fifoStatusRegisterContents.bits.RX_EMPTY != 1)
  176. {
  177. messageReceived = true;
  178. }
  179. nrfInterruptRaised = false;
  180. }
  181. // Set the NRF to standby
  182. NRF_CE_PORT &= ~(1 << NRF_CE_PIN);
  183. configRegisterContents.byte = Read_NRF_Register(CONFIG_ADDRESS);
  184. configRegisterContents.bits.PRIM_RX = 0x0;
  185. Write_NRF_Register(CONFIG_ADDRESS, configRegisterContents.byte);
  186. PCICR &= ~(1<<PCIE2); // Disable the interrupt for the IRQ signal
  187. if (messageReceived == true)
  188. {
  189. Read_Message_From_RX_FIFO(PACKET_LENGTH, buffer); /* TODO: only possible after CE = 0? */
  190. }
  191. /* Reset the interrupts */
  192. statusRegisterContents.bits.TX_DS = 1;
  193. statusRegisterContents.bits.MAX_RT = 1;
  194. statusRegisterContents.bits.RX_DR = 1;
  195. Write_NRF_Register(STATUS_ADDRESS, statusRegisterContents.byte);
  196. return messageReceived;
  197. }
  198. uint8_t Read_NRF_Status_Register(void)
  199. {
  200. uint8_t registerContents;
  201. registerContents = Write_One_Byte(0x0);
  202. return registerContents;
  203. }
  204. uint8_t Read_NRF_Register(uint8_t address)
  205. {
  206. uint8_t registerContents;
  207. registerContents = Write_Two_Bytes(address, 0x0);
  208. return registerContents;
  209. }
  210. void Write_NRF_Register(uint8_t address, uint8_t registerContents)
  211. {
  212. Write_Two_Bytes(address | 0x20, registerContents);
  213. }
  214. void Send_Activate_Command(void)
  215. {
  216. Write_Two_Bytes(0x50, 0x73);
  217. }
  218. void Send_TX_Flush_Command(void)
  219. {
  220. Write_One_Byte(FLUSH_TX_COMMAND);
  221. }
  222. void Send_RX_Flush_Command(void)
  223. {
  224. Write_One_Byte(FLUSH_RX_COMMAND);
  225. }
  226. static uint8_t Write_One_Byte(uint8_t byte1)
  227. {
  228. uint8_t registerContents = 0;
  229. SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  230. registerContents = SPI_Transfer_Byte(byte1);
  231. SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  232. return registerContents;
  233. }
  234. static uint8_t Write_Two_Bytes(uint8_t byte1, uint8_t byte2)
  235. {
  236. uint8_t registerContents = 0;
  237. SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  238. SPI_Transfer_Byte(byte1);
  239. registerContents = SPI_Transfer_Byte(byte2);
  240. SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  241. return registerContents;
  242. }
  243. void Write_Message_To_TX_FIFO(uint8_t length, uint8_t * buffer)
  244. {
  245. Write_Byte_And_Buffer(W_TX_PAYLOAD_COMMAND, buffer, length);
  246. }
  247. void Read_Message_From_RX_FIFO(uint8_t length, uint8_t * buffer)
  248. {
  249. SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  250. SPI_Transfer_Byte(R_RX_PAYLOAD_COMMAND);
  251. /* Write the data byte */
  252. for (uint8_t i = 0; i < length; i ++)
  253. {
  254. buffer[i] = SPI_Transfer_Byte(0x0);
  255. }
  256. SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  257. }
  258. void Set_TX_Address(uint8_t * txAddress, uint8_t length)
  259. {
  260. Write_Byte_And_Buffer(TX_ADDR_ADDRESS | 0x20, txAddress, length);
  261. }
  262. void Set_RX_P0_Address(uint8_t * rxAddress, uint8_t length)
  263. {
  264. Write_Byte_And_Buffer(RX_ADDR_P0_ADDRESS | 0x20, rxAddress, length);
  265. }
  266. void Set_RX_P1_Address(uint8_t * rxAddress, uint8_t length)
  267. {
  268. Write_Byte_And_Buffer(RX_ADDR_P1_ADDRESS | 0x20, rxAddress, length);
  269. }
  270. static void Write_Byte_And_Buffer(uint8_t byte, uint8_t * buffer, uint8_t length)
  271. {
  272. SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  273. SPI_Transfer_Byte(byte);
  274. /* Write the data byte */
  275. for (uint8_t i = 0; i < length; i ++)
  276. {
  277. SPI_Transfer_Byte(buffer[i]);
  278. }
  279. SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
  280. }