#ifndef NRF24L01_DEFINITIONS_H
#define NRF24L01_DEFINITIONS_H


/* NRF24L01 register mnemonic definitions */
#define CONFIG 0x0
#define EN_AA 0x1
#define EN_RXADDR 0x2
#define SETUP_AW 0x3
#define SETUP_RETR 0x4
#define RF_CH 0x5
#define RF_SETUP 0x6
#define STATUS 0x7
#define OBSERVE_TX 0x8
#define CD 0x9
#define RX_ADDR_P0 0xA
#define RX_ADDR_P1 0xB
#define RX_ADDR_P2 0xC
#define RX_ADDR_P3 0xD
#define RX_ADDR_P4 0xE
#define RX_ADDR_P5 0xF
#define TX_ADDR 0x10
#define RX_PW_P0 0x11
#define RX_PW_P1 0x12
#define RX_PW_P2 0x13
#define RX_PW_P3 0x14
#define RX_PW_P4 0x15
#define RX_PW_P5 0x16
#define FIFO_STATUS 0x17
#define DYNPD 0x1C
#define FEATURE 0x1D

/* Register bits definitions */
/* CONFIG*/
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t bit012 : 3;
		 uint8_t bit34 : 2;
		 uint8_t bit5 : 1;
		 uint8_t bit6 : 1;
		 uint8_t bit7 : 1;
	}bits;
}CONFIG_REGISTER;

#define MASK_RX_DR (1<<6)
#define MASK_TX_DS (1<<5)
#define MASK_MAX_RT (1<<4)
#define EN_CRC (1<<3)
#define CRCO (1<<2)
#define PWR_UP (1<<1)
#define PRIM_RX (1<<0)

/*EN_AA */
#define ENAA_P5 (1<<5)
#define ENAA_P4 (1<<4)
#define ENAA_P3 (1<<3)
#define ENAA_P2 (1<<2)
#define ENAA_P1 (1<<1)
#define ENAA_P0 (1<<0)

/* EN_RXADDR */
#define ERX_P5 (1<<5)
#define ERX_P4 (1<<4)
#define ERX_P3 (1<<3)
#define ERX_P2 (1<<2)
#define ERX_P1 (1<<1)
#define ERX_P0 (1<<0)


#define  (1<<)
#define  (1<<)
#define  (1<<)
#define  (1<<)
#define  (1<<)
#define  (1<<)
#define  (1<<)
#define  (1<<)

#endif