#ifndef NRF24L01_DEFINITIONS_H
#define NRF24L01_DEFINITIONS_H

#define MAX_ADDRESS_LENGTH 5

/* NRF24L01 register mnemonic definitions */
#define CONFIG_ADDRESS 0x0
#define EN_AA_ADDRESS 0x1
#define EN_RXADDR_ADDRESS 0x2
#define SETUP_AW_ADDRESS 0x3
#define SETUP_RETR_ADDRESS 0x4
#define RF_CH_ADDRESS 0x5
#define RF_SETUP_ADDRESS 0x6
#define STATUS_ADDRESS 0x7
#define OBSERVE_TX_ADDRESS 0x8
#define CD_ADDRESS 0x9
#define RX_ADDR_P0_ADDRESS 0xA
#define RX_ADDR_P1_ADDRESS 0xB
#define RX_ADDR_P2_ADDRESS 0xC
#define RX_ADDR_P3_ADDRESS 0xD
#define RX_ADDR_P4_ADDRESS 0xE
#define RX_ADDR_P5_ADDRESS 0xF
#define TX_ADDR_ADDRESS 0x10
#define RX_PW_P0_ADDRESS 0x11
#define RX_PW_P1_ADDRESS 0x12
#define RX_PW_P2_ADDRESS 0x13
#define RX_PW_P3_ADDRESS 0x14
#define RX_PW_P4_ADDRESS 0x15
#define RX_PW_P5_ADDRESS 0x16
#define FIFO_STATUS_ADDRESS 0x17
#define DYNPD_ADDRESS 0x1C
#define FEATURE_ADDRESS 0x1D

/* Commands */
#define FLUSH_TX_COMMAND 0xE1
#define FLUSH_RX_COMMAND 0xE2
#define W_TX_PAYLOAD_COMMAND 0xA0
#define R_RX_PAYLOAD_COMMAND 0x61

/* Register bits definitions */
/* CONFIG*/
typedef union
{
	uint8_t byte;
	struct
	{
		uint8_t PRIM_RX     : 1;
		uint8_t PWR_UP      : 1;
		uint8_t CRCO        : 1;
		uint8_t EN_CRC      : 1;
		uint8_t MASK_MAX_RT : 1;
		uint8_t MASK_TX_DS  : 1;
		uint8_t MASK_RX_DR  : 1;
		uint8_t RESERVED    : 1;
	}bits;
}CONFIG_REGISTER;

/*EN_AA */
typedef union
{
	uint8_t byte;
	struct
	{
		uint8_t ENAA_P0  : 1;
		uint8_t ENAA_P1  : 1;
		uint8_t ENAA_P2  : 1;
		uint8_t ENAA_P3  : 1;
		uint8_t ENAA_P4  : 1;
		uint8_t ENAA_P5  : 1;
		uint8_t RESERVED : 2;
	}bits;
}EN_AA_REGISTER;

/* EN_RXADDR */
typedef union
{
	uint8_t byte;
	struct
	{
		uint8_t ERX_P0   : 1;
		uint8_t ERX_P1   : 1;
		uint8_t ERX_P2   : 1;
		uint8_t ERX_P3   : 1;
		uint8_t ERX_P4   : 1;
		uint8_t ERX_P5   : 1;
		uint8_t RESERVED : 2;
	}bits;
}EN_RXADDR_REGISTER;

/* SETUP_AW */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t AW : 2;
		 uint8_t RESERVED : 6;
	}bits;
}SETUP_AW_REGISTER;

#define ADDRESS_WIDTH_3_BYTES 0x1
#define ADDRESS_WIDTH_4_BYTES 0x2
#define ADDRESS_WIDTH_5_BYTES 0x3

/* SETUP_RETR */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t ARC : 4;
		 uint8_t ARD : 4;
	}bits;
}SETUP_RETR_REGISTER;

/* RF_CH */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t RF_CH : 7;
		 uint8_t RESERVED : 1;
	}bits;
}RF_CH_REGISTER;

/* RF_SETUP */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t LNA_HCURR : 1;
		 uint8_t RF_PWR    : 2;
		 uint8_t RF_DR     : 1;
		 uint8_t PLL_LOCK  : 1;
		 uint8_t RESERVED  : 3;
	}bits;
}RF_SETUP_REGISTER;

#define RF_DATA_RATE_1MBPS 0x0
#define RF_DATA_RATE_2MBPS 0x1

#define RF_OUTPUT_POWER_MINUS_18DBM
#define RF_OUTPUT_POWER_MINUS_12DBM
#define RF_OUTPUT_POWER_MINUS_16DBM
#define RF_OUTPUT_POWER_0DBM

// TODO: change order of all bit fields!!!

/* STATUS */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t TX_FULL  : 1;
		 uint8_t RX_P_NO  : 3;
		 uint8_t MAX_RT   : 1;
		 uint8_t TX_DS    : 1;
		 uint8_t RX_DR    : 1;
		 uint8_t RESERVED : 1;
	}bits;
}STATUS_REGISTER;

#define RX_FIFO_EMPTY 0x7

/* OBSERVE_TX */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t ARC_CNT  : 4;
		 uint8_t PLOS_CNT : 4;
	}bits;
}OBSERVE_TX_REGISTER;

/* CD */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t CD : 1;
		 uint8_t RESERVED : 7;
	}bits;
}CD_REGISTER;

/* RX_PW_Pn */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t RESERVED : 2;
		 uint8_t RX_PW_Pn : 6;
	}bits;
}RX_PW_Pn_REGISTER;

/* FIFO_STATUS */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t RX_EMPTY : 1;
		 uint8_t RX_FULL  : 1;
		 uint8_t RESERVED1 : 2;
		 uint8_t TX_EMPTY : 1;
		 uint8_t TX_FULL  : 1;
		 uint8_t TX_REUSE : 1;
		 uint8_t RESERVED0 : 1;
	}bits;
}FIFO_STATUS_REGISTER;

/* DYNPD */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t DPL_P0   : 1;
		 uint8_t DPL_P1   : 1;
		 uint8_t DPL_P2   : 1;
		 uint8_t DPL_P3   : 1;
		 uint8_t DPL_P4   : 1;
		 uint8_t DPL_P5   : 1;
		 uint8_t RESERVED : 2;
	}bits;
}DYNPD_REGISTER;

/* FEATURE */
typedef union
{
	uint8_t byte;
	struct
	{
		 uint8_t EN_DYN_ACK : 1;
		 uint8_t EN_ACK_PAY : 1;
		 uint8_t EN_DPL     : 1;
		 uint8_t RESERVED   : 5;
	}bits;
}FEATURE_REGISTER;

#endif