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@@ -17,9 +17,13 @@
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extern volatile bool nrfInterruptRaised;
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void Print_Register_Contents(uint8_t address);
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+
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+
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void Send_TX_Flush_Command(void);
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+void Send_RX_Flush_Command(void);
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24
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22
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-static void Write_Two_Bytes(uint8_t byte1, uint8_t byte2);
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+static uint8_t Write_One_Byte(uint8_t byte1);
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+static uint8_t Write_Two_Bytes(uint8_t byte1, uint8_t byte2);
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static void Write_Byte_And_Buffer(uint8_t byte, uint8_t * buffer, uint8_t length);
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/* Startup and initial configuration of the NRF24L01 */
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@@ -72,28 +76,7 @@ void Configure_Transmission(uint8_t moduleId)
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76
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DYNPD_REGISTER dyndpRegisterContents = {.byte = 0x0};
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73
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uint8_t txAddress[5] = {0xB3, 0xB3, 0xB3, 0xB3, 0x00};
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- uint8_t rx0Address[5] = {0xB3, 0xB3, 0xB3, 0xB3, 0x00};
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76
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- /*
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77
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- * - Length of CRC (CRCO in CONFIG)
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78
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- * - Enable auto acknowledgment (EN_AA)
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79
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- * -> Register already set correctly after reset
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- * - Enable data pipes (EN_RXADDR)?
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81
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- * -> Two pipes are already enabled on reset
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- * - Set up address width (SETUP_AW)
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- * -> 3 bytes
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- * - Automatic Retransmission (SETUP_RETR)
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85
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- * -> ARD = 0b0000
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86
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- * -> 3 retransmits -> ARC = 0b0011
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87
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- * -> Register already set correctly after reset
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- * - RF Channel (RF_CH)
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- * -> RF_CH = 0b1010000
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- * - RF Setup (RF_SETUP)
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91
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- * -> first use reset values, can be fine tuned later
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92
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- * - Enable dynamic payload length (DYNPD) -> command activate + 0x73, then set bits in FEATURE?
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- */
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94
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-
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- /* Set the address width to 3 bytes */
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- //Write_NRF_Register(0x03, 0x1);
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+ uint8_t rx1Address[5] = {0xB3, 0xB3, 0xB3, 0xB3, 0x00};
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81
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/* Set the frequency to 1450 MHz */
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Write_NRF_Register(RF_CH_ADDRESS, 0x32);
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@@ -116,8 +99,6 @@ void Configure_Transmission(uint8_t moduleId)
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Write_NRF_Register(DYNPD_ADDRESS, dyndpRegisterContents.byte);
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100
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/* Set up the auto retries */
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-
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- /* */
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setupRetrRegisterContents.bits.ARC = 0x3;
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setupRetrRegisterContents.bits.ARD = 0xF;
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Write_NRF_Register(SETUP_RETR_ADDRESS, setupRetrRegisterContents.byte);
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@@ -125,20 +106,54 @@ void Configure_Transmission(uint8_t moduleId)
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/* Set the TX address */
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Set_TX_Address(txAddress, MAX_ADDRESS_LENGTH);
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108
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- /* Set the RX_P0 address to the one of the base station to receive acks */
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- Set_RX_P0_Address(rx0Address, MAX_ADDRESS_LENGTH);
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+ /* Set the address of the RX pipe 0 to the one of the base station to receive acks */
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+ Set_RX_P0_Address(txAddress, MAX_ADDRESS_LENGTH);
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+
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+ /* Set the address of the RX pipe 1 to the own address to receive messages */
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+ rx1Address[4] = moduleId; // The last byte of the address corresponds to the Id set by the pin programming
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+ Set_RX_P1_Address(rx1Address, MAX_ADDRESS_LENGTH);
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+
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+ /* Enable the rx addresses for pipe 0 and pipe 1*/
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+ enableRxAddressesRegisterContents.bits.ERX_P0 = 1;
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+ enableRxAddressesRegisterContents.bits.ERX_P1 = 1;
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+ Write_NRF_Register(EN_RXADDR_ADDRESS, enableRxAddressesRegisterContents.byte);
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+
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+ /* Set the payload witth for pipe 1 */
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+ rxPwPnRegisterContents.bits.RX_PW_Pn = 32;
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+ Write_NRF_Register(RX_PW_P1_ADDRESS, rxPwPnRegisterContents.byte);
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+
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+ rxPwPnRegisterContents.bits.RX_PW_Pn = 0;
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+ Write_NRF_Register(RX_PW_P0_ADDRESS, rxPwPnRegisterContents.byte); // auto-ack pipe
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+ Write_NRF_Register(RX_PW_P2_ADDRESS, rxPwPnRegisterContents.byte); // not used
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+ Write_NRF_Register(RX_PW_P3_ADDRESS, rxPwPnRegisterContents.byte); // not used
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+ Write_NRF_Register(RX_PW_P4_ADDRESS, rxPwPnRegisterContents.byte); // not used
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+ Write_NRF_Register(RX_PW_P5_ADDRESS, rxPwPnRegisterContents.byte); // not used
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+
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+ /* Enable auto acknowledge for pipe 1 */
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+ enAaRegister.bits.ENAA_P0 = 1;
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+ enAaRegister.bits.ENAA_P1 = 1;
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+ enAaRegister.bits.ENAA_P2 = 1;
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+ enAaRegister.bits.ENAA_P3 = 1;
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+ enAaRegister.bits.ENAA_P4 = 1;
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+ enAaRegister.bits.ENAA_P5 = 1;
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+ Write_NRF_Register(EN_AA_ADDRESS, enAaRegister.byte);
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+
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+ /* Flush FIFOs */
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+ Send_TX_Flush_Command();
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+ Send_RX_Flush_Command();
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144
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145
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PCMSK2 |= (1<<PCINT21); // Set the external interrupt for PD5
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}
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148
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-void NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
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+bool NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
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150
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{
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+ bool success = false;
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STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
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153
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if ((length > 32) || (length == 0))
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{
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- return;
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+ return success;
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}
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158
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159
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PCICR |= (1<<PCIE2); // Enable the interrupt for the IRQ signal
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@@ -155,7 +170,6 @@ void NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
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155
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170
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* induced by the SPI:
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171
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* https://forum.mysensors.org/topic/10452/nrf24l01-communication-failure-root-cause-and-solution
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*/
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- LED_PORT |= (1 << LED_PIN);
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statusRegisterContents.byte = Read_NRF_Status_Register();
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175
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@@ -164,6 +178,10 @@ void NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
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{
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Send_TX_Flush_Command(); /* Remove the packet from the TX FIFO as it is not done automatically */
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}
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+ else
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+ {
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+ success = true;
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+ }
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/* Reset the interrupts */
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@@ -176,57 +194,88 @@ void NRF24L01_Send_Message(uint8_t *buffer, uint8_t length)
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194
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nrfInterruptRaised = false;
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- return;
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+ return success;
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}
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-uint8_t Read_NRF_Status_Register(void)
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+bool NRF24L01_Receive_Message(uint8_t *buffer, uint8_t duration)
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{
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- uint8_t registerContents;
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+ uint8_t messageReceived = false;
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+ CONFIG_REGISTER configRegisterContents = {.byte = 0x0};
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+ STATUS_REGISTER statusRegisterContents = {.byte = 0x0};
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+ FIFO_STATUS_REGISTER fifoStatusRegisterContents = {.byte = 0x0};
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206
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- SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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- registerContents = SPI_Transfer_Byte(0x00);
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- SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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- return registerContents;
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-}
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+ PCICR |= (1<<PCIE2); // Enable the interrupt for the IRQ signal
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208
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+ // Enable the receive mode
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+ configRegisterContents.byte = Read_NRF_Register(CONFIG_ADDRESS);
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+ configRegisterContents.bits.PRIM_RX = 0x1;
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+ Write_NRF_Register(CONFIG_ADDRESS, configRegisterContents.byte);
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192
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213
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193
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-/* TODO: rewrite the read register function if it is needed (remove the read operations for the 5-byte registers)*/
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194
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-#if 0
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195
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-uint8_t Read_NRF_Register(uint8_t address, uint8_t * registerContents)
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196
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-{
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197
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- /* TODO: simplify this function, as the registers with more than one byte are accessed with other functions */
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- uint8_t numberOfBytes = 0;
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199
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214
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200
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- if ((address == 0x0A) ||
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201
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- (address == 0x0B) ||
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202
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- (address == 0x10))
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215
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+ NRF_CE_PORT |= (1 << NRF_CE_PIN);
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+
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217
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+ _delay_ms(10);
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+ while ((nrfInterruptRaised == false) && (duration > 0))
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{
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204
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- numberOfBytes = 5;
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- }
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- else
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220
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+ _delay_ms(1);
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+ duration --;
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+ };
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+
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+ if (nrfInterruptRaised == true) // check if a message was received
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207
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225
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{
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208
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- numberOfBytes = 1;
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226
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+ /* A message was received */
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+
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228
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+ statusRegisterContents.byte = Read_NRF_Status_Register();
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229
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+
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230
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+ fifoStatusRegisterContents.byte = Read_NRF_Register(FIFO_STATUS_ADDRESS);
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231
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+ if (fifoStatusRegisterContents.bits.RX_EMPTY != 1)
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232
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+ {
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233
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+ messageReceived = true;
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234
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+ }
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+
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236
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+ nrfInterruptRaised = false;
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237
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}
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210
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238
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211
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- /* First write the address */
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212
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- SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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239
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+ // Set the NRF to standby
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240
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+ NRF_CE_PORT &= ~(1 << NRF_CE_PIN);
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213
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241
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242
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+ configRegisterContents.byte = Read_NRF_Register(CONFIG_ADDRESS);
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243
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+ configRegisterContents.bits.PRIM_RX = 0x0;
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244
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+ Write_NRF_Register(CONFIG_ADDRESS, configRegisterContents.byte);
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214
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245
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215
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- SPI_Transfer_Byte(address);
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246
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+ PCICR &= ~(1<<PCIE2); // Disable the interrupt for the IRQ signal
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216
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247
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217
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- /* Read the register bytes */
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218
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- for (uint8_t i = 0; i < numberOfBytes; i++)
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248
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+ if (messageReceived == true)
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219
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249
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{
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220
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- /* Write dummy data to shift in the register content */
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221
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- registerContents[i] = SPI_Transfer_Byte(0x0);
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250
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+ Read_Message_From_RX_FIFO(PACKET_LENGTH, buffer); /* TODO: only possible after CE = 0? */
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222
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251
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}
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223
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252
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224
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- SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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253
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+ /* Reset the interrupts */
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254
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+ statusRegisterContents.bits.TX_DS = 1;
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255
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+ statusRegisterContents.bits.MAX_RT = 1;
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256
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+ statusRegisterContents.bits.RX_DR = 1;
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257
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+ Write_NRF_Register(STATUS_ADDRESS, statusRegisterContents.byte);
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225
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258
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226
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- return numberOfBytes;
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259
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+ return messageReceived;
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227
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260
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}
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228
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261
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229
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-#endif
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262
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+uint8_t Read_NRF_Status_Register(void)
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263
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+{
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264
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+ uint8_t registerContents;
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265
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+
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266
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+ registerContents = Write_One_Byte(0x0);
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267
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+ return registerContents;
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268
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+}
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269
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+
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270
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+
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271
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+uint8_t Read_NRF_Register(uint8_t address)
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272
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+{
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273
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+ uint8_t registerContents;
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274
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+
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275
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+ registerContents = Write_Two_Bytes(address, 0x0);
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276
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+
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277
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+ return registerContents;
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278
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+}
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230
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279
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231
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280
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void Write_NRF_Register(uint8_t address, uint8_t registerContents)
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232
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281
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{
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@@ -238,31 +287,59 @@ void Send_Activate_Command(void)
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238
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287
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Write_Two_Bytes(0x50, 0x73);
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239
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288
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}
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240
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289
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241
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-static void Write_Two_Bytes(uint8_t byte1, uint8_t byte2)
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290
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+void Send_TX_Flush_Command(void)
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291
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+{
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292
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+ Write_One_Byte(FLUSH_TX_COMMAND);
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293
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+}
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294
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+
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|
295
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+void Send_RX_Flush_Command(void)
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|
296
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+{
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297
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+ Write_One_Byte(FLUSH_RX_COMMAND);
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298
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+}
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299
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+
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|
300
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+static uint8_t Write_One_Byte(uint8_t byte1)
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242
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301
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{
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302
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+ uint8_t registerContents = 0;
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243
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303
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SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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244
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304
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245
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- SPI_Transfer_Byte(byte1);
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246
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- SPI_Transfer_Byte(byte2);
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305
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+ registerContents = SPI_Transfer_Byte(byte1);
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247
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306
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248
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307
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SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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308
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+ return registerContents;
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249
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309
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}
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250
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310
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251
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-void Send_TX_Flush_Command(void)
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311
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+static uint8_t Write_Two_Bytes(uint8_t byte1, uint8_t byte2)
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|
252
|
312
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{
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253
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- /* First write the write command with the address */
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313
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+ uint8_t registerContents = 0;
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254
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314
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SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
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255
|
315
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|
256
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- SPI_Transfer_Byte(0xE1);
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316
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+ SPI_Transfer_Byte(byte1);
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317
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+ registerContents = SPI_Transfer_Byte(byte2);
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257
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318
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258
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319
|
SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
|
|
|
320
|
+ return registerContents;
|
|
259
|
321
|
}
|
|
260
|
322
|
|
|
261
|
323
|
|
|
262
|
324
|
|
|
263
|
325
|
void Write_Message_To_TX_FIFO(uint8_t length, uint8_t * buffer)
|
|
264
|
326
|
{
|
|
265
|
|
- Write_Byte_And_Buffer(0xA0, buffer, length);
|
|
|
327
|
+ Write_Byte_And_Buffer(W_TX_PAYLOAD_COMMAND, buffer, length);
|
|
|
328
|
+}
|
|
|
329
|
+
|
|
|
330
|
+void Read_Message_From_RX_FIFO(uint8_t length, uint8_t * buffer)
|
|
|
331
|
+{
|
|
|
332
|
+ SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
|
|
|
333
|
+
|
|
|
334
|
+ SPI_Transfer_Byte(R_RX_PAYLOAD_COMMAND);
|
|
|
335
|
+
|
|
|
336
|
+ /* Write the data byte */
|
|
|
337
|
+ for (uint8_t i = 0; i < length; i ++)
|
|
|
338
|
+ {
|
|
|
339
|
+ buffer[i] = SPI_Transfer_Byte(0x0);
|
|
|
340
|
+ }
|
|
|
341
|
+
|
|
|
342
|
+ SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
|
|
266
|
343
|
}
|
|
267
|
344
|
|
|
268
|
345
|
void Set_TX_Address(uint8_t * txAddress, uint8_t length)
|
|
|
@@ -275,6 +352,11 @@ void Set_RX_P0_Address(uint8_t * rxAddress, uint8_t length)
|
|
275
|
352
|
Write_Byte_And_Buffer(RX_ADDR_P0_ADDRESS | 0x20, rxAddress, length);
|
|
276
|
353
|
}
|
|
277
|
354
|
|
|
|
355
|
+void Set_RX_P1_Address(uint8_t * rxAddress, uint8_t length)
|
|
|
356
|
+{
|
|
|
357
|
+ Write_Byte_And_Buffer(RX_ADDR_P1_ADDRESS | 0x20, rxAddress, length);
|
|
|
358
|
+}
|
|
|
359
|
+
|
|
278
|
360
|
static void Write_Byte_And_Buffer(uint8_t byte, uint8_t * buffer, uint8_t length)
|
|
279
|
361
|
{
|
|
280
|
362
|
SPI_Start_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
|
|
|
@@ -289,5 +371,3 @@ static void Write_Byte_And_Buffer(uint8_t byte, uint8_t * buffer, uint8_t length
|
|
289
|
371
|
|
|
290
|
372
|
SPI_Stop_Transmission(&NRF_CSN_PORT, NRF_CSN_PIN);
|
|
291
|
373
|
}
|
|
292
|
|
-
|
|
293
|
|
-//TODO: only write the used bytes into the address registers & add generic write functions
|